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dcr820n65 phase control thyristor preliminary information ds5923-1.3 june 2008 (ln 26210) 1/11 www.dynexsemi.com features double side cooling high surge capability applications medium voltage soft starts high voltage power supplies static switches voltage ratings part and ordering number repetitive peak voltages v drm and v rrm v conditions dcr820n65* DCR820N60 dcr820n55 dcr820n50 6500 6000 5500 5000 t vj = -40c to 125c, i drm = i rrm = 200ma, v drm , v rrm t p = 10ms, v dsm & v rsm = v drm & v rrm + 100v respectively lower voltage grades available. 6200v @ -40 0 c, 6500v @ 0 0 c ordering information when ordering, select the required part number shown in the voltage ratings selection table. for example: dcr820n65 note: please use the complete part number when orde ring and quote this number in any future correspondence relating to your order. key parameters v drm 6500v i t(av) 820a i tsm 12000a dv/dt* 1500v/s di/dt 200a/s * higher dv/dt selections available outline type code: n (see package details for further information) fig. 1 package outline
semiconductor dcr820n65 2/11 www.dynexsemi.com current ratings t case = 60c unless stated otherwise symbol parameter test conditions max. units double side cooled i t(av) mean on-state current half wave resistive load 820 a i t(rms) rms value - 1288 a i t continuous (direct) on-state current - 1090 a surge ratings symbol parameter test conditions max. units i tsm surge (non-repetitive) on-state current 10ms half si ne, t case = 125c 12.0 ka i 2 t i 2 t for fusing v r = 0 0.72 ma 2 s thermal and mechanical ratings symbol parameter test conditions min. max. units r th(j-c) thermal resistance ? junction to case double side co oled dc - 0.0221 c/w single side cooled anode dc - 0.041 c/w cathode dc - 0.0516 c/w r th(c-h) thermal resistance ? case to heatsink clamping force 23 kn double side - 0.004 c/w (with mounting compound) single side - 0.008 c/w t vj virtual junction temperature on-state (conducting) - 1 35 c reverse (blocking) - 125 c t stg storage temperature range -55 125 c f m clamping force 20.0 25.0 kn
semiconductor dcr820n65 3/11 www.dynexsemi.com dynamic characteristics symbol parameter test conditions min. max. units i rrm /i drm peak reverse and off-state current at v rrm /v drm , t case = 125c - 200 ma dv/dt max. linear rate of rise of off-state voltage t o 67% v drm , t j = 125c, gate open - 1500 v/s di/dt rate of rise of on-state current from 67% v drm to 2x i t(av) repetitive 50hz - 100 a/s gate source 30v, 10 , non-repetitive - 200 a/s t r < 0.5s, t j = 125c v t(to) threshold voltage ? low level 100a to 870a at t case = 125c - 1.0 v threshold voltage ? high level 870a to 3000a at t case = 125c - 1.1847 v r t on-state slope resistance ? low level 100a to 870a a t t case = 125c - 1.1429 m on-state slope resistance ? high level 870a to 3000a at t case = 125c - 0.9472 m t gd delay time v d = 67% v drm , gate source 30v, 10 - 3 s t r = 0.5s, t j = 25c t q turn-off time t j = 125c,i peak = 1000a, t p = 1000us, v rm = 100v, di/dt = -5a/s, 600 1000 s dv dr /dt = 20v/s linear to 2500v i rr reverse recovery current 90 120 a q s stored charge i t = 1000a, t p = 1000us,t j = 125c, di/dt = - 5a/s, v r = 100v 2500 4000 c i l latching current t j = 25c, v d = 5v - 3 a i h holding current t j = 25c, r g-k = , i tm = 500a, i t = 5a - 300 ma
semiconductor dcr820n65 4/11 www.dynexsemi.com gate trigger characteristics and ratings symbol parameter test conditions max. units v gt gate trigger voltage v drm = 5v, t case = 25c 1.5 v v gd gate non-trigger voltage at 50% v drm, t case = 125c 0.4 v i gt gate trigger current v drm = 5v, t case = 25c 250 ma i gd gate non-trigger current at 50% v drm, t case = 125c 15 ma curves 0 500 1000 1500 2000 2500 3000 3500 1.0 2.0 3.0 4.0 5.0 instantaneous on-state voltage, v t - (v) instantaneous on-state current, i t - (a) min 25c 25c max 125c min 125c max fig.2 maximum & minimum on-state characteristics v tm equation where a = 0.739446 b = 0.018199 v tm = a + bln (i t ) + c.i t +d. i t c = 0.000769 d = 0.017564 these values are valid for t j = 125c for i t 300a to 3000a
semiconductor dcr820n65 5/11 www.dynexsemi.com 0 2 4 6 8 10 12 14 16 0 500 1000 1500 2000 2500 mean on-state current, i t(av) - (a) mean power dissipation - (kw) 180 120 90 60 30 0 25 50 75 100 125 0 500 1000 1500 mean on-state current, i t(av) - (a) maximum case temperature, t case ( o c ) 180 120 90 60 30 fig.3 on-state power dissipation ? sine wave fig.4 m aximum permissible case temperature, double side cooled ? sine wave 0 25 50 75 100 125 0 500 1000 1500 mean on-state current, i t(av) - (a) maximum heatsink temperature, t heatsink - ( c) 180 120 90 60 30 0 2 4 6 8 10 12 14 16 0 1000 2000 3000 4000 mean on-state current, i t(av) - (a) mean power dissipation - (kw) d.c. 180 120 90 60 30 fig.5 maximum permissible heatsink temperature, double side cooled ? sine wave fig.6 on-state power dissipation ? rectangular wav e
semiconductor dcr820n65 6/11 www.dynexsemi.com 0 25 50 75 100 125 0 500 1000 1500 2000 mean on-state current, i t(av) - (a) maximum permissible case temperature , t case -( c) d.c. 180 120 90 60 30 0 25 50 75 100 125 0 500 1000 1500 2000 mean on-state current, i t(av ) - (a) maximum heatsink temperature t heatsink -( o c) d.c. 180 120 90 60 30 fig.7 maximum permissible case temperature, double side cooled ? rectangular wave fig.8 maximum permissible heatsink temperature, double side cooled ? rectangular wave 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 0.001 0.01 0.1 1 10 100 time ( s ) thermal impedance, z th(j-c) ( c/kw ) zth double side cooled zth cathode side cooled zth anode side cooled 1 2 3 4 double side cooled r i (c/kw) 3.4733 4.9047 9.1463 4.5220 t i (s) 0.1457 0.0166 1.2832 0.3767 anode side cooled r i (c/kw) 7.6674 5.0530 9.7355 27.5992 t i (s) 0.2241 0.0169 4.0566 8.2780 cathode side cooled r i (c/kw) 6.0393 4.2782 5.1301 25.0874 t i (s) 0.1356 0.0143 0.6594 7.2358 )] / exp( 1( [ 4 1 i i i i th t t r z r th(j-c) conduction tables show the increments of thermal resistance r th(j-c) when the device operates at conduction angles other than d.c. double side cooling anode side cooling cathode sided cooling z th (z) z th (z) z th (z) sine. rect. sine. rect. sine. rect. 180 3.03 2.07 180 3.03 2.07 180 3.12 2.12 120 3.49 2.95 120 3.49 2.95 120 3.61 3.04 90 3.99 3.43 90 3.99 3.43 90 4.13 3.54 60 4.43 3.94 60 4.43 3.94 60 4.60 4.08 30 4.77 4.49 30 4.76 4.48 30 4.96 4.66 15 4.92 4.77 15 4.92 4.77 15 5.13 4.97 fig.9 maximum (limit) transient thermal impedance ? junction to case (c/kw)
semiconductor dcr820n65 7/11 www.dynexsemi.com 0 10 20 30 1 10 100 pulse width, t p - (ms) surge current, i tsm - (ka) 0 0.5 1 1.5 i 2 t (ma 2 s) i 2 t i tsm conditions: t case = 125c v r = 0 half-sine wave 1 10 100 1 10 100 number of cycles surge current, i tsm - (ka) conditions: tcase = 125c v r =0 pulse width = 10ms fig.10 single-cycle surge current fig.11 multi-cycle surge current 0 1000 2000 3000 4000 5000 6000 7000 8000 0 20 40 60 rate of decay of on-state current, di/dt - (a/us) stored charge, q s - (uc) q smax = 2550.9*(di/dt) 0.2795 q smin = 1325.8(di/dt) 0.3941 conditions : i f = 1000a t p = 1000us v rm = 100v t j = 125 o c 0 100 200 300 400 500 600 0 10 20 30 40 50 60 rate of decay of on-state current, di/dt - (a/us) reverse recovery current, i rr - (a) i rrmax = 41.65*(di/dt) 0.6452 i rrmin = 28.33*(di/dt) 0.7182 conditions: i f = 1000a t p = 1000us v rm = 100v t j = 125 o c fig.12 stored charge fig.13 reverse recovery current
semiconductor dcr820n65 8/11 www.dynexsemi.com 0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 gate trigger current i gt , - (a) gate trigger voltage, v gt - (v) tj = 125 o c tj = 25 o c tj = -40 o c preferred gate drive area upper limit lower limit fig14 gate characteristics 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 9 10 gate trigger current, i gt - (a) gate trigger voltage, v gt - (v) lower limit upper limit 5w 10w 20w 50w 100w 150w -40c fig. 15 gate characteristics 50 100 400 100 150 150 150 200 150 150 125 500 150 150 100 1000 150 100 25 10000 20 - - pulse width us frequency hz pulse power p gm (watts)
semiconductor dcr820n65 9/11 www.dynexsemi.com 0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 0 20 40 60 80 100 120 rate of change of reapplied voltage, dv/dt - (v/us) normalised turn-off time, tq - (us) t q (dv/dt) = t q(20v/us). 0.7148.(dv/dt) 0.1124 conditions: t j = 125 o c i f = 1000a t p = 1000us v rm = 100v di/dt = -5a/us fig.16 turn-off time
semiconductor dcr820n65 10/11 www.dynexsemi.com package details for further package information, please contact cus tomer services. all dimensions in mm, unless state d otherwise. do not scale. hole ?3.60 x 2.00 electrodes) deep (in both ?73.0 max ?47.0 nom ?47.0 nom ? 1 . 5 gate anode cathode 3rd angle projection if in doubt ask do not scale 20 offset (nom.) to gate tube for package height see table device maximum thickness (mm) minimum thickness (mm) dcr1710n22 34.465 33.915 dcr1530n28 34.54 33.99 dcr1260n42 34.77 34.22 dcr1110n52 34.89 34.34 dcr820n65 35.15 34.6 dcr890n65 35.15 34.6 dcr760n85 35.51 34.96 lead length: 420mm lead terminal connector: m4 ring package outline type code: n fig.17 package outline
semiconductor dcr820n65 11/11 www.dynexsemi.com power assembly capability the power assembly group was set up to provide a su pport service for those customers requiring more th an the basic semiconductor, and has developed a flexible range o f heatsink and clamping systems in line with advanc es in device voltages and current capability of our semiconductors. we offer an extensive range of air and liquid coole d assemblies covering the full range of circuit des igns in general use today. the assembly group offers high quality engineering support dedicated to designing new units to satisfy the growing needs of our customers. using the latest cad methods our team of design and applications engineers aim to provide the power as sembly complete solution (pacs). heatsinks the power assembly group has its own proprietary ra nge of extruded aluminium heatsinks which have been designed to optimise the performance of dynex semiconductors. data with respect to air natural, forced air and liquid cool ing (with flow rates) is available on request. for further information on device clamps, heatsinks and assemblies, please contact your nearest sales representative or customer services. stresses above those listed in this data sheet may cause permanent damage to the device. in extreme c onditions, as with all semiconductors, this may include potentially hazard ous rupture of the package. appropriate safety pre cautions should always be followed. http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com headquarters operations customer service dynex semiconductor ltd tel: +44(0)1522 502753 / 502901. fax: +44(0)1522 50 0020 doddington road, lincoln lincolnshire, ln6 3lf. united kingdom. tel: +44(0)1522 500500 fax: +44(0)1522 500550 dynex semiconductor 2003 technical documentation ? not for resale. produced in united kingdom. this publication is issued to provide information only wh ich (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form pa rt of any order or contract nor to be regarded as a representation relatin g to the products or services concerned. no warranty or gu arantee express or implied is made regarding the capab ility, performance or suitability of any product or service. the company reserv es the right to alter without prior notice the specif ication, design or price of any product or service. inf ormation concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility to fully determine the performance and suitability of any e quipment using such information and to ensure that any p ublication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant inj ury or death to the user. all products and materials ar e sold and services provided subject to the company?s conditions of sale, which are ava ilable on request. all brand names and product names used in this publicatio n are trademarks, registered trademarks or trade names of their respective owners.

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